Prior art personal computer systems typically employ removable data storage media. One common prior art removable storage medium is a floppy disk. A relatively new prior art storage medium is an integrated circuit-based memory card ("IC memory card").
Prior art flash erasable and electrically programmable read-only memory ("flash EPROM")is nonvolatile and reprogrammable, and this has permitted the flash EPROM technology to be used for removable data storage. One such prior art application is the flash EPROM memory card ("flash memory card"). The flash memory card typically includes a number of flash EPROMs. The flash memory card can be erased and programmed electrically.
FIG. 1 illustrates a prior art flash memory card 10. As can be seen from FIG. 1, flash memory card 10 includes a memory array 11 and a card control logic 15. Memory array 11 includes a number of flash EPROMs 11a through 11n. Card control logic 15 interfaces memory array 11 with external host computer.
As can be seen from FIG. 1, each of flash EPROMs 11a-11n typically includes a ready/busy output pin RY/BY. Ready/busy RY/BY is the ready/busy indicator of each of flash EPROMs 11a-11n. A logical high RY/BY output of a flash EPROM indicates a "ready" condition or mode for the flash EPROM (i.e., ready to accept an operation). A logical low RY/BY output indicates a "busy" condition or mode for the flash EPROM. Typically, a flash EPROM includes a control circuit that controls the memory operations of the flash EPROM. The "busy" condition or mode for the flash EPROM means that the control circuit of the flash EPORM is presently busy in performing the programming or erasure operation.
As also can be seen from FIG. 1, card control logic 15 includes ready/busy registers 16 and associated gating logic (not shown) for applying a card ready/busy output signal RDY/BSY to the external circuitry. The number of registers 16 corresponds to the member of flash EPROMs 11a-11n in memory array 11. Each of registers 16 receives a ready/busy RY/BY signal from the RY/BY output of the corresponding flash EPROM. A signal line (i.e., one of signal lines 12a through 12n)is connected between one of registers 16 and the RY/BY output pin of the respective flash EPROM for transferring the RY/BY signal to that register from the associated flash EPROM.
The provision of the ready/busy registers in the card control logic to store the ready/busy RY/BY signal from each of the flash EPROMs allows the card control logic to selectively mask out the ready/busy RY/BY signal from any one of the flash EPROMs inside the prior art flash memory card. As is known, the RY/BY signal of a flash EPROM is an active low signal when the control circuit of the flash EPROM is busy performing either a programming operation or an erasure operation. However, the time for the programming operation is typically much less than that for the erasure operation. Therefore, the busy indication of the RY/BY signal can be ignored (i.e., masked) when the respective flash EPROM is undergoing the programming operation. When the RY/BY signal of a particular flash EPROM is masked, then the ready/busy status of that particular flash EPROM will have no effect on the card ready/busy output RDY/BSY of the card control logic. The mask function is typically accomplished by the gating logic (not shown) associated with the ready/busy registers.
In addition, card control logic 15 of prior flash memory card 10 of FIG. 1 also includes power control registers 17, each storing the power control signal PWD for its respective one of flash EPROMs 11a-11n. A signal line (i.e., one of signal lines 13a-13n) is connected to one of power control registers 17 and its respective one of flash EPROMs 11a-11n for supplying the power control signal PWD to the respective flash EPROM.
One disadvantage of the prior flash memory card is that the flash memory card typically requires separate signal lines to transfer the individual ready/busy RY/BY signals to the ready/busy registers inside the card control logic. This typically causes the pin count of the card control logic to increase which typically occupies large die space of the card control logic. In addition, the card control logic needs to provide the ready/busy registers to latch the individual ready/busy signal from each of the flash EPROMs. This typically occupies relatively large die space of the card control logic and complicates the logic of the card control logic. Moreover, the software running in the card control logic is typically complicated. This is because during a normal memory operation, both (1) the attribute memory region of the flash memory card that contains the ready/busy registers and (2) the common memory region of the card that includes the flash EPROMs need to be accessed.
Furthermore, the prior art scheme of providing the individual power control signal PWD as shown in FIG. 1 also bears the disadvantage of excessive pin count for the card control logic and complex logic in the card control logic. As shown in FIG. 1, power control registers 17 includes a number of registers such that each of flash EPROMs 11a-11n receives an individual power control PWD signal.